L7200 datasheet(13/23 Pages) STMICROELECTRONICS

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L7200

BIT

LABEL

DESCRIPTION

INDEX

External FLL update.

EXTK

“0” Spindle Speed internal KFLL. “1” All Reg#7 and Lsb of Reg#8 bits are

mixed to allow external setting of KFLL.

MECH/ELEC

Electrical or Mechanical cycle for Spindle FLL control.

“0” Mechanical. “1” Electrical.

8_12POLE

Spindle Motor Poles. “0” 8 poles. “1” 12 poles.

Reg:

Name:

Spindle Set-Up 2 Register

Type:

Write only

Address: 3Eh

BIT

LABEL

DESCRIPTION

ZCWINDOW

Chop cycle for Spindle ZC tristate time. “0” Two. “1” One.

REVBRAKE

“1” Spindle Reverse Brake. Toggling this bit will define the time before

ending over normal brake. 1 = 10mS. 2 = 20mS. 3 = 40mS.

CLKDIV

SYSCLK divider. “0” SYSCLK. “1” SYSCLK divide by 2.

DIV1.5

SYSCLK divider. “0” SYSCLK. “1” SYSCLK divide by 1.5.

FLLCOARSE<0>

LSB of Spindle FLL Coarse Counter.

FLLCOARSE<1>

Bit 1 of Spindle FLL Coarse Counter.

FLLCOARSE<2>

Bit 2 of Spindle FLL Coarse Counter.

FLLCOARSE<3>

Bit 3 of Spindle FLL Coarse Counter.

Reg:

Name:

Spindle FLL Coarse Register

Type:

Write only

Address: 4Eh

BIT

LABEL

DESCRIPTION

FLLCOARSE<4>

Bit 4 of Spindle FLL Coarse Counter.

FLLCOARSE<5>

Bit 5 of Spindle FLL Coarse Counter.

FLLCOARSE<6>

Bit 6 of Spindle FLL Coarse Counter.

FLLCOARSE<7>

Bit 7 of Spindle FLL Coarse Counter.

FLLCOARSE<8>

Bit 8 of Spindle FLL Coarse Counter.

FLLCOARSE<9>

Bit 9 of Spindle FLL Coarse Counter.

INTERNAL REGISTERS DEFINITION (continued)

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