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PCI2250 Datasheet(PDF) 41 Page - Texas Instruments |
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PCI2250 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 85 page  4–7 4.11 Base Address Register 0 The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Base address register 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Base address register 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Base address register 0 Type: Read-only Offset: 10h Default: 0000 0000h 4.12 Base Address Register 1 The bridge requires no additional resources. Base address register 1 is read-only and returns 0s when read. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Base address register 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Base address register 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Base address register 1 Type: Read-only Offset: 14h Default: 0000 0000h 4.13 Primary Bus Number Register The primary bus number register indicates the primary bus number to which the bridge is connected. The bridge uses this register, in conjunction with the secondary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses. Bit 7 6 5 4 3 2 1 0 Name Primary bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Primary bus number Type: Read/write Offset: 18h Default: 00h |
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