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PCI2250 Datasheet(PDF) 46 Page - Texas Instruments |
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PCI2250 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 85 page  4–12 4.23 Prefetchable Memory Limit Register The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31–AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Prefetchable memory limit Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Prefetchable memory limit Type: Read-only, read/write Offset: 26h Default: 0000h 4.24 Prefetchable Base Upper 32 Bits Register The PCI2250 does not support 64-bit addressing; thus, the prefetchable base upper 32-bit register is read-only and returns 0s when read. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Prefetchable base upper 32 bits Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Prefetchable base upper 32 bits Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Prefetchable base upper 32 bits Type: Read-only Offset: 28h Default: 0000 0000h 4.25 Prefetchable Limit Upper 32 Bits Register The PCI2250 does not support 64-bit addressing; thus the prefetchable limit upper 32-bit register is read-only and returns 0s when read. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Prefetchable limit upper 32 bits Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Prefetchable limit upper 32 bits Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Prefetchable limit upper 32 bits Type: Read-only Offset: 2Ch Default: 0000 0000h |
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