ST7921

Ver 1.6

7/11

2005/05/24

Functional Description :

Clock

The CL1 is the clock to latch data on the falling edge. It latches the data input from the bi-directional

shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is

the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers

the output of each bit of the register to the latch circuit.

Shift Registers And Data I/O

The ST7921 supplies two sets of 48-bit shift register, which controls the shift direction by SHL1 &

SHL2. The SHL1 controls the 1st 48-bit shift register, and SHL2 controls the 2nd 48-bit shift register.

When SHL1 is connected to VDD, the 1st shift direction is from S48 to S1; when SHL1 is connected

to VSS, the shift direction changes from S1 to S48. When SHL2 is connected to VDD, the 2nd shift

direction is from S96 to S49; when SHL2 is connected to VSS, the shift direction changes from S49

to S96.

The DL1, DR1, DL2, DR2 are data input or output option function.

Shift Direction of Channel 1

SHL1

Shift Direction

DL1

DR1

0

S1

S48

IN

OUT

1

S48

S1

OUT

IN

Shift Direction of Channel 2

SHL2

Shift Direction

DL2

DR2

0

S49

S96

IN

OUT

1

S96

S49

OUT

IN