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PE43701 Datasheet(PDF) 9 Page - Peregrine Semiconductor |
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PE43701 Datasheet(HTML) 9 Page - Peregrine Semiconductor |
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9 / 13 page  Product Specification PE43701 Page 9 of 13 Document No. 70-0243-06 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Table 12. Parallel and Direct Interface AC Characteristics Table 11. Serial-Addressable Interface AC Characteristics Note: fClk is verified during the functional pattern test. Serial- Addressable programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified Figure 20. Serial-Addressable Timing Diagram Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram Symbol Parameter Min Max Unit FCLK Serial clock frequency - 10 MHz TCLKH Serial clock HIGH time 30 - ns TCLKL Serial clock LOW time 30 - ns TLESU Last serial clock rising edge setup time to Latch Enable rising edge 10 - ns TLEPW Latch Enable min. pulse width 30 - ns TSISU Serial data setup time 10 - ns TSIH Serial data hold time 10 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TASU Address setup time 100 - ns TAH Address hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Symbol Parameter Min Max Unit TLEPW Latch Enable minimum pulse width 30 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSIH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns TDIPD Digital register delay (internal, direct mode only) - 5 ns VALID T DISU T DIH DI[6:0] LE P/S T PSSU T PSH T LEPW VALID DO[6:0] T DIPD T PD A[2] A[1] A[0] T SISU T CLKL T LEPW T SIH T CLKH SI CLK LE P/S T LESU T PSSU T PSIH VALID T ASU ADD[2:0] T AIH DO[6:0] VALID DI[6:0] T PD T DISU T DIH D[6] D[5] D[4] D[3] D[2] D[1] D[0] *D[7] *D[7] must be set to logic low Bits can either be set to logic high or logic low Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com |
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