Product Specification

PE43701

Page 10 of 13

©2008-2009 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0243-06

│ UltraCMOS™ RFIC Solutions

Evaluation Kit

The Digital Attenuator Evaluation Kit board was

designed to ease customer evaluation of the

PE43701 Digital Step Attenuator.

Direct-Parallel Programming Procedure

For automated direct-parallel programming,

connect the test harness provided with the EVK

from the parallel port of the PC to the J1 & Serial

header pin and set the D0-D6 SP3T switches to the

‘MIDDLE’ toggle position. Position the Parallel/

Serial (

P̅/S) select switch to the Parallel (or left)

position. The evaluation software is written to

operate the DSA in either Parallel or Serial-

Addressable Mode. Ensure that the software is set

to program in Direct-Parallel mode. Using the

software, enable or disable each setting to the

desired attenuation state. The software

automatically programs the DSA each time an

attenuation state is enabled or disabled.

For manual direct-parallel programming,

disconnect the test harness provided with the EVK

from the J1 and Serial header pins. Position the

Parallel/Serial (

P̅/S) select switch to the Parallel (or

left) position. The LE pin on the Serial header must

which enable the user to manually program the

parallel bits. When any input D0-D6 is toggled

‘UP’, logic high is presented to the parallel input.

When toggled ‘DOWN’, logic low is presented to

the parallel input. Setting D0-D6 to the ‘MIDDLE’

toggle position presents an OPEN, which forces an

on-chip logic low. Table 9 depicts the parallel

programming truth table and Fig. 21 illustrates the

parallel programming timing diagram.

Latched-Parallel Programming Procedure

For automated latched-parallel programming, the

procedure is identical to the direct-parallel method.

The user only must ensure that Latched-Parallel is

selected in the software.

For manual latched-parallel programming, the

procedure is identical to direct-parallel except now

the LE pin on the Serial header must be logic low

as the parallel bits are applied. The user must then

programming word into the DSA. LE must be logic

low prior to programming the next word.

Figure 22. Evaluation Board Layout

Peregrine Specification 101-0312

Serial-Addressable Programming Procedure

Position the Parallel/Serial (

P̅/S) select switch to

the Serial (or right) position. Prior to

programming, the user must define an address

setting using the ADD header pin. Jump the

middle pins on the ADD header A0-A2 (or lower)

row of pins to set logic high, or jump the middle

pins to the upper row of pins to set logic low. If

the ADD pins are left open, then 000 become the

default address. The evaluation software is

written to operate the DSA in either Parallel or

Serial-Addressable Mode. Ensure that the

software is set to program in Serial-Addressable

mode. Using the software, enable or disable each

setting to the desired attenuation state. The

software automatically programs the DSA each

time an attenuation state is enabled or disabled.

Note: Reference Fig. 23 for Evaluation Board Schematic

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