PM0214 datasheet(111/245 Pages) STMICROELECTRONICS

111 / 245 page

DocID022708 Rev 4

111/245

PM0214

The STM32 Cortex-M4 instruction set

244

UMLAL

R2, R1, R3, R5

; Multiplies R5 and R3, adds R1:R2, writes to R1:R2.

3.6.3

SMLA and SMLAW

Signed multiply accumulate (halfwords).

Syntax

op{XY}{cond} Rd, Rn, Rm

op{Y}{cond} Rd, Rn, Rm, Ra

where

•

op is one of:

SMLA: Signed multiply accumulate long (halfwords). X and Y specifies which half of the

source registers Rn and Rm are used as the first and second multiply operand.

–

If X is B, then the bottom halfword, bits [15:0], of Rn is used.

–

If X is T, then the top halfword, bits [31:16], of Rn is used.

–

If Y is B, then the bottom halfword, bits [15:0], of Rm is used.

–

If Y is T, then the top halfword, bits [31:16], of Rm is used.

SMLAW: Signed multiply accumulate (word by halfword). Y specifies which half of the

source register Rm is used as the second multiply operand.

–

If Y is T, then the top halfword, bits [31:16] of Rm is used.

–

If Y is B, then the bottom halfword, bits [15:0] of Rm is used.

•

‘cond’ is an optional condition code (see Conditional execution on page 64)

•

‘Rd’ is the destination register. If Rd is omitted, the destination register is Rn

•

‘Rn’, ‘Rm’ are registers holding the values to be multiplied

•

‘Ra’ is a register holding the value to be added to or subtracted from

Operation

The SMALBB, SMLABT, SMLATB, SMLATT instructions:

Multiply the specified signed halfword, top or bottom, values from Rn and Rm.

Add the value in Ra to the resulting 32-bit product.

Write the result of the multiplication and addition in Rd.

The non-specified halfwords of the source registers are ignored.

The SMLAWB and SMLAWT instructions:

Multiply the 32-bit signed values in Rn with:

The top signed halfword of Rm, T instruction suffix.

The bottom signed halfword of Rm, B instruction suffix.

Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product

Write the result of the multiplication and addition in Rd.

The bottom 16 bits of the 48-bit product are ignored.

If overflow occurs during the addition of the accumulate value, the instruction sets the

Q flag in the APSR. No overflow can occur during the multiplication.

Restrictions

In these instructions, do not use SP or PC.

Condition flags

PM0214 Datasheet(PDF) 111 Page - STMicroelectronics

PM0214 Datasheet(HTML) 111 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL