SM5842AP/APT

NIPPON PRECISION CIRCUITS—3

PIN DESCRIPTION

Number

Name

Description

1

DI/INF2N

Ip

Data input when INF1N is LOW, and input format select pin 2 when INF1N is HIGH.

2

BCKI

Ip

Input bit clock

3

CKSLN

Ip

Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW.

4

INF1N

Ip

Input format select pin 1. INF1N and INF2N select the pin functions below.

5

IW1N/DIL

Ip

Input bit length select pin 1 when INF1N is LOW, and left-channel data input when INF1N is HIGH.

IW1N and IW2N select the input data length.

6

XTI

I

Oscillator input connection

7

XTO

O

Oscillator output connection

8

VSS

–

Ground

9

CKO

O

Oscillator output clock. Same frequency as XTI.

10

IW2N/DIR

Ip

Input bit length select pin 2 when INF2N is LOW, and right-channel data input when INF2N is HIGH.

IW1N and IW2N select the input data length as shown in the table for pin 5.

11

OW1N

Ip

Output length select bits.

12

OW2N

Ip

13

SYNCN

Ip

Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH.

14

RSTN

Ip

System reset. Reset operation when LOW, and normal operation when HIGH.

15

DEMPR

Ip

Right-channel deemphasis control signal. OFF when LOW, and ON when HIGH.

16

DEMPR

Ip

Left-channel deemphasis control signal. OFF when LOW, and ON when HIGH.

17

FSEL1

Ip

Deemphasis filter select inputs

18

FSEL2

Ip

INF1N

DI/INF2N

Input format

Pin function selection

DI/INF2N

IW1N/DIL

IW2N/DIR

LOW

LOW

LR alternating, trailing data

DI

IW1N

IW2N

LOW

HIGH

HIGH

LOW

LR alternating, leading data

INF2N

DIL

DIR

HIGH

HIGH

LR simultaneous, leading data

INF1N

IW2N/DIL

IW1N/DIR

Input bit length

LOW

LOW

LOW

24 bits

LOW

HIGH

20 bits

HIGH

LOW

18 bits

HIGH

HIGH

16 bits

HIGH

××

24 bits

OW2N

OW1N

Output bit length

LOW

LOW

24 bits

LOW

HIGH

22 bits

HIGH

LOW

20 bits

HIGH

HIGH

18 bits

FSEL1

FSEL2

Sampling frequency (fs)

LOW

LOW

44.1 kHz

LOW

HIGH

48 kHz

HIGH

LOW

Invalid setting

HIGH

HIGH

32 kHz