SM5842AP datasheet(16/23 Pages) NPC

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SM5842AP/APT

NIPPON PRECISION CIRCUITS—16

System Reset (RSTN)

Under

normal

operating

conditions,

the

SM5842AP/APT does not need to be reset. However,

it can be reset when you want to synchronize the

LRCI clock and internal operation timing in jitter-

free mode.

The system is reset by applying a LOW-level pulse

on RSTN.

The arithmetic and output timing counters are reset

on the ﬁrst LRCI start edge after reset is released, as

long as the XTI clock has already stabilized. The

LRCI start edge is determined by the state of INF1N

and INF2N. When INF1N is LOW or when both

INF1N and INF2N are HIGH, the start edge is the

rising edge. When INF1N is HIGH and INF2N is

LOW, the start edge is the falling edge.

When RSTN is LOW, the DOL and DOR outputs are

LOW, muting the output signal to an attenuation

level of

−∞.

The power-ON reset pulse can be applied by a

microcontroller or, for systems where XTI and LRCI

are stable at power-ON, by connecting a capacitor of

about 300 pF between RSTN and VSS. For systems

that do not use a microcontroller, the capacitor must

be chosen such that the XTI and LRCI clocks fully

stabilize before RSTN goes from LOW to HIGH.

Figure 3. System reset timing and output muting

RSTN

LRCI

DOL

DOR

Internal reset

WCKO

SM5842AP Datasheet(PDF) 16 Page - Nippon Precision Circuits Inc