REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

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Interrupt Status Register (10h) / Reset Interrupt Status Register (11h)

The Interrupt Status Register is used to determine the source of an interrupt event. When an interrupt event occurs in the

ADE7754, the corresponding flag in the Interrupt Status Register is set logic high. The IRQ pin will go active low if the

corresponding bit in the Interrupt Mask register is set logic high. When the MCU services the interrupt, it must first carry

out a read from the Interrupt Status Register to determine the source of the interrupt. All the interrupts in the Interrupt Status

Register stay at their logic high state after an event occurs. The state of the interrupt bit in the Interrupt Status register is reset

to its default value once the Reset Interrupt Status register is read.

Table XVII STATUS Register

Bit

Interrupt

Default

Event

Location

Flag

Value

Description

0

AEHF

0

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the AENERGY

register (i.e. the AENERGY register is half-full)

1

SAGA

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A

2

SAGB

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B

3

SAGC

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C

4

ZXTOA

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the

Phase A

5

ZXTOB

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the

Phase B

6

ZXTOC

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the

Phase C

7

Z X A

0

Indicates a detection of rising zero crossing in the voltage channel of the phase A

8

Z X B

0

Indicates a detection of rising zero crossing in the voltage channel of the phase B

9

Z X C

0

Indicates a detection of rising zero crossing in the voltage channel of the phase C

Ah

LENERGY

0

In Line energy accumulation, it indicates the end of an integration over an integer number

of half line cycles (LINCYC) —see Energy Calibration

B h

RESET

0

Indicates that the ADE7754 has been reset

C h

PKV

0

Indicates that an interrupt was caused when the selected voltage input is above the value

in the PKVLV register.

D h

PKI

0

Indicates that an interrupt was caused when the selected current input is above the value

in the PKILV register.

E h

WFSM

0

Indicates that new data is present in the Waveform Register.

F h

VAEHF

0

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the

VAENERGY register (i.e. the VAENERGY register is half-full)

INTERRUPT STATUS REGISTER*

ADDR: 10h

0

1

2

3

4

5

6

7

00

0

0

0

0

0

0

8

9

A

B

C

D

E

F

00

0

0

0

0

0

0

VAEHF

(Apparent Energy Register Half Full)

AEHF

(Active Energy Register Half Full)

SAG

(SAG Event Detect)

WFMP

(New Waveform Sample Ready)

*Register contents show power on defaults

ZX

(Zero Crossing Time out Detection)

PKV

LENERGY

(End of the LAENERGY and LVAENERGY accumulation)

ZX

(Zero Crossing Detection)

RESET

PKI

(Current channel Peak detection)

(Voltage channel Peak detection)