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AX88655AB Datasheet(PDF) 8 Page - ASIX Electronics Corporation

Part # AX88655AB
Description  5-Port 10/100/1000BASE-T Ethernet Switch
PDF  33 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88655AB Datasheet(HTML) 8 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
8
AX88655AB 5-Port 10/100/1000BASE-T Ethernet Switch
CONFIDENTIAL
COL1
I/PD
D18
Collision Detect: Please references section 2.1.1.
CRS1
I/PD
D19
Carrier Sense: Please references section 2.1.1.
RX_DV1
I
E19
Receive Data Valid: Please references section 2.1.1.
RX_CLK1
I
E18
Receive Clock Input: Please references section 2.1.1.
RXD1[7:0]
I/PD
E20, F17, F18,
F19, F20, G17,
G18, G19
Receive Data: Please references section 2.1.1.
2.1.6 RGMII/GMII/MII Interface Port 2
Signal Name
I/O
Pin No.
Description
GTX_CLK2
O
A18
125MHz Clock Output: Please references section 2.1.1.
TX_EN2
O
B18
Transmit Enable: Please references section 2.1.1.
TXD2[7:0]
O
C18, B19, A19,
A20, B20, C19,
C20, D20
Transmit Data: Please references section 2.1.1.
TX_CLK2
I/PD
C15
MII Transmit Clock Input: Please references section 2.1.1.
COL2
I/PD
D15
Collision Detect: Please references section 2.1.1.
CRS2
I/PD
D14
Carrier Sense: Please references section 2.1.1.
RX_DV2
I
A15
Receive Data Valid: Please references section 2.1.1.
RX_CLK2
I
B15
Receive Clock Input: Please references section 2.1.1.
RXD2[7:0]
I/PD
D16, C16, B16,
A16, D17,
C17, B17, A17
Receive Data: Please references section 2.1.1.
2.1.7 RGMII/GMII/MII Interface Port 3
Signal Name
I/O
Pin No.
Description
GTX_CLK3
O
A11
125MHz Clock Output: Please references section 2.1.1.
TX_EN3
O
C12
Transmit Enable: Please references section 2.1.1.
TXD3[7:0]
O
B12, A12, C13,
B13, A13, C14,
B14, A14
Transmit Data: Please references section 2.1.1.
TX_CLK3
I/PD
D9
MII Transmit Clock Input: Please references section 2.1.1.
COL3
I/PD
C8
Collision Detect: Please references section 2.1.1.
CRS3
I/PD
D8
Carrier Sense: Please references section 2.1.1.
RX_DV3
I
B9
Receive Data Valid: Please references section 2.1.1.
RX_CLK3
I
C9
Receive Clock Input: Please references section 2.1.1.
RXD3[7:0]
I/PD
A9, D10, C10,
B10, A10,
D11, C11, B11
Receive Data: Please references section 2.1.1.
2.1.8 RGMII/GMII/MII Interface Port 4
Signal Name
I/O
Pin No.
Description
GTX_CLK4
O
A5
125MHz Clock Output: Please references section 2.1.1.
TX_EN4
O
B5
Transmit Enable: Please references section 2.1.1.



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