| Electronic Components Datasheet Search |
|
L6986H Datasheet(PDF) 39 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L6986H Datasheet(HTML) 39 Page - STMicroelectronics |
|
39 / 68 page ![]() 5.5 Compensation network design The maximum bandwidth of the system can be designed up to fSW/6 up to 150 kHz maximum to guarantee a valid small signal model. RC=2⋅π⋅BW⋅COUT⋅VOUT 0.85V⋅gCS⋅gm TYP (33) where: fPOLE= ωp2⋅π (34) ωp is defined by , gCS represents the current sense transconductance (see Table 1) and gm TYP the error amplifier transconductance. CC= 5 2⋅π⋅RC⋅BW (35) Example 2: Considering VIN = 12 V, VOUT = 3.3 V, L = 6.8 µH, COUT = 10 µF, fSW = 500 kHz, IOUT = 1 A. The maximum system bandwidth is 80 kHz. Assuming to design the compensation network to achieve a system bandwidth of 70 kHz: fPOLE=2.7 kHz (36) RLOAD=VOUTIOUT=3.3Ω (37) so accordingly with Eq. (33) and Eq. (35): RC=48.5kΩ≈47kΩ (38) CC=237pF≈270pF (39) The gain and phase bode diagrams are plotted respectively in Figure 40. Magnitude plot for example 2 and Figure 41. Phase plot for example 2. Figure 40. Magnitude plot for example 2 L6986H Compensation network design DS12905 - Rev 2 page 39/68 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |