TC7135CPL datasheet(13/24 Pages) MICROCHIP

13 / 24 page

 2004 Microchip Technology Inc.

DS21460C-page 13

TC7135

TABLE 6-2:

LINE FREQUENCY

REJECTION VS. CLOCK

FREQUENCY

The conversion rate is easily calculated:

EQUATION 6-3:

6.3

High Speed Operation

The maximum conversion rate of most dual-slope A/D

converters is limited by the frequency response of the

comparator. The comparator in this circuit follows the

integrator ramp with a 3 µsec delay, at a clock

frequency of 160 kHz (6 µsec period). Half of the first

reference integrate clock period is lost in delay. This

means that the meter reading will change from 0 to 1

with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV,

etc. This transition at midpoint is considered desirable

by most users. However, if the clock frequency is

increased appreciably above 200 kHz, the instrument

will flash "1" on noise peaks, even when the input is

shorted.

For many dedicated applications where the input signal

is always of one polarity, the delay of the comparator

need not be a limitation. Since the nonlinearity and

noise do not increase substantially with frequency, clock

rates of up to ~1 MHz may be used. For a fixed clock

frequency, the extra count (or counts) caused by

comparator delay will be a constant and can be

subtracted out digitally.

The clock frequency may be extended above 160 kHz

without this error, however, by using a low value

resistor in series with the integrating capacitor. The

effect of the resistor is to introduce a small pedestal

voltage on to the integrator output at the beginning of

the reference integrate phase. By careful selection of

the ratio between this resistor and the integrating

resistor (a few tens of ohms in the recommended

circuit), the comparator delay can be compensated and

the

maximum

clock

frequency

extended

approximately a factor of 3. At higher frequencies,

ringing and second-order breaks will cause significant

nonlinearities in the first few counts of the instrument.

The minimum clock frequency is established by

leakage on the auto-zero and reference capacitors.

With most devices, measurement cycles as long as 10

seconds give no measurable leakage error.

The clock used should be free from significant phase or

frequency jitter. Several suitable low-cost oscillators

are shown in Section 6.0 “Typical Applications”. The

multiplexed output means that if the display takes

significant current from the logic supply, the clock

should have good PSRR.

6.4

Zero Crossing Flip Flop

The flip flop interrogates the data once every clock

pulse after the transients of the previous clock pulse and

half clock pulse have died down. False zero crossings

caused by clock pulses are not recognized. Of course,

the flip flop delays the true zero crossing by up to one

count in every instance. If a correction were not made,

the display would always be one count too high.

Therefore, the counter is disabled for one clock pulse at

the beginning of the reference integrate (de-integrate)

phase. This one-count delay compensates for the delay

of the zero crossing flip flop and allows the correct

number to be latched into the display. Similarly, a one-

count delay at the beginning of auto-zero gives an

overload display of 0000 instead of 0001. No delay

occurs during signal integrate so that true ratiometric

readings result.

6.5

Generating a Negative Supply

A negative voltage can be generated from the positive

supply by using a TC7135 (see Figure 6-1).

FIGURE 6-1:

Negative Supply Voltage

Generator.

Oscillator Frequency

(kHz)

Line Frequency

Rejection

(Hz)

300

200

150

120

100

33-1/3

250

166-2/3

125

100

50, 60,400

Reading 1/sec

Clock Frequency (Hz)

4000

-----------------------------------------------------

TC7660

TC7135

+5V

(-5V)

V+

V–

10 µF

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