ADF4206BRUZ-R7 datasheet(12/24 Pages) AD

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ADF4206/ADF4208

Rev. A | Page 12 of 24

CONTROL

MUX

DVDD

MUXOUT

DGND

RF2 ANALOG LOCK DETECT

RF2 R COUNTER OUTPUT

RF2 N COUNTER OUTPUT

RF2/RF1 ANALOG LOCK DETECT

RF1 R COUNTER OUTPUT

RF1 N COUNTER OUTPUT

RF1 ANALOG LOCK DETECT

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter (N =

BP + A) and produces an output proportional to the phase and

frequency difference between them. Figure 25 is a simplified

schematic.

DELAY

ELEMENT

CLR2

CLR1

CHARGE

PUMP

DOWN

R DIVIDER

N DIVIDER

CP OUTPUT

R DIVIDER

N DIVIDER

CPGND

Figure 26. MUXOUT Circuit

LOCK DETECT

MUXOUT can be programmed for analog lock detect. The

N-channel open-drain analog lock detect is operated with an

external pull-up resistor of 10 kΩ nominal. When lock is

detected, it is high with narrow, low going pulses.

INPUT SHIFT REGISTER

The functional block diagram for the ADF420x family is shown

in Figure 1. The main blocks include a 22-bit input shift register,

a 14-bit R counter, and a 17-bit N counter, comprising a 6-bit

A counter and an 11-bit B counter. Data is clocked into the

22-bit shift register on each rising edge of CLK. The data is

clocked in MSB first. Data is transferred from the shift register

to one of four latches on the rising edge of LE. The destination

latch is determined by the state of the two control bits (C2, C1)

in the shift register. These are the two LSBs (DB1, DB0) as

shown in the timing diagram of Figure 2.

Table 5 is the truth table for these bits.

Table 5. C2, C1 Truth Table

Figure 25. PFD Simplified Schematic and Timing (In Lock)

The PFD includes a delay element that sets the width of the

antibacklash phase. The typical value for this in the ADF420x

family is 3 ns. The pulse ensures that there is no dead zone in

the PFD transfer function and minimizes phase noise and

reference spurs.

Control Bits

Data Latch

RF2 R counter

RF2 AB counter (and prescaler select)

RF1 R counter

RF1 AB counter (and prescaler select)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4206 family allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by P3, P4, P11, and P12. See Figure 28

and Figure 30. Figure 26 shows the MUXOUT circuit in block

diagram form.

ADF4206BRUZ-R7 Datasheet(PDF) 12 Page - Analog Devices

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