ADF4206BRUZ-R7 datasheet(22/24 Pages) AD

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ADF4206/ADF4208

Rev. A | Page 22 of 24

INTERFACING

The ADF420x family has a simple SPI®-compatible serial inter-

face for writing to the device. CLK, DATA, and LE control the

data transfer. When LE goes high, the 22 bits clocked into the

input register on each rising edge of CLK transfers to the

appropriate latch. See Figure 2 for the timing diagram and

Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

909 kHz or one update every 1.1 ms. This is more than adequate

for systems that have typical lock times in hundreds of

microseconds.

ADuC812 INTERFACE

Figure 34 shows the interface between the ADF420x family and

the ADuC812 microconverter. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF420x family

needs a 22-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

On first applying power to the ADF420x family, it requires four

writes (one each to the R counter latch and the AB counter latch

for both RF1 and RF2 sides) for the output to become active.

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed

will be about 180 kHz.

SCLOCK

MOSI

I/O PORTS

ADuC812

CLK

DATA

MUXOUT

(LOCK DETECT)

ADF4206/

ADF4208

Figure 34. ADuC812 to ADF420x Family Interface

ADSP-2181 INTERFACE

Figure 35 shows the interface between the ADF420x family and

the ADSP-21xx digital signal processor. The ADF420x family

needs a 22-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP21-xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for eight bits and use three memory locations for each

22-bit word. To program each 22-bit latch, store the three 8-bit

bytes, enable the autobuffered mode and then write to the

transmit register of the DSP. This last operation initiates the

autobuffer transfer.

SCLK

I/O FLAG

ADSP-21xx

CLK

DATA

MUXOUT

(LOCK DETECT)

ADF4206/

ADF4208

TFS

Figure 35. ADSP-21xx to ADF420x Family Interface

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