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74LVC595AD Datasheet(PDF) 12 Page - Nexperia B.V. All rights reserved |
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74LVC595AD Datasheet(HTML) 12 Page - Nexperia B.V. All rights reserved |
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12 / 20 page ![]() © Nexperia B.V. 2017. All rights reserved 74LVC595A All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 20 June 2014 12 of 20 Nexperia 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. 3-state enable and disable times 001aae821 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OE input VI VCC VM VOL VOH GND GND tPZL tPZH VM VM Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY VCC <2.7 V 0.5 V CC 0.5 V CC VOL 0.15 V VOH 0.15 V VCC 2.7 V 1.5 V 1.5 V VOL 0.3 V VOH 0.3 V |
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