Product Specification

SP4306

Page 8 of 10

B5

B4

B3

B2

B1

B0

C16

C8C4C2

C1

0

↑↑

LSB (last in)

MSB (first in)

Table 7. 5-Bit Attenuator Serial Programming

Register Map

Table 9. Parallel Interface AC Characteristics

Figure 18. Parallel Interface Timing Diagram

Table 8. Serial Interface AC Characteristics

Figure 17. Serial Interface Timing Diagram

Note: The stop bit (B0) must always be low to prevent the attenuator

from entering an unknown state.

programming sections of the functional pattern are clocked at

10 MHz to verify fclk specification.

LE

Clock

Data

MSB

LSB

t

LESUP

t

SDSUP

t

SDHLD

t

LEPW

t

PDSUP

t

PDHLD

LE

t

LEPW

Parallel Data

C16:C1

Symbol

Parameter

Min

Max

Unit

Serial data clock

frequency (Note 1)

10

MHz

Serial clock HIGH time

30

ns

Serial clock LOW time

30

ns

LE set-up time after last

clock falling edge

10

ns

LE minimum pulse width

30

ns

Serial data set-up time

before clock rising edge

10

ns

Serial data hold time

after clock falling edge

10

ns

Symbol

Parameter

Min

Max

Unit

LE minimum pulse width

10

ns

Data set-up time before

rising edge of LE

10

ns

Data hold time after

falling edge of LE

10

ns

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