Product Specification

SP43701

Page 7 of 12

Table 6. Latch and Clock Specifications

Table 5. Control Voltage

State

Bias Condition

Low

0 to +1.0 Vdc at 2

µA (typ)

High

+2.6 to +5 Vdc at 10

µA (typ)

Table 7. Parallel Truth Table

Table 10. Serial-Addressable Register Map

Q15

Q14

Q13

Q12

Q11

Q10

A7

A6

A5

A4

A3

A2

Q9

Q8

Q7

Q6

Q5

Q4

A1

A0

D7

D6

D5

D4

Q3

Q2

Q1

Q0

D3

D2

D1

D0

Address Word

Attenuation Word

LSB (first in)

MSB (last in)

Bits can either be set to logic high or logic low

Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state

at address 3:

Address word: XXXXX011

Attenuation Word: Multiply by 4 and convert to binary

→ 4 * 18.25 dB → 73 → X1001001

Serial Input: XXXXX011X1001001

Latch Enable

Function

0

Shift Register Clocked

↑

Contents of shift register

transferred to attenuator core

Shift Clock

↑

X

Parallel Control Setting

Attenuation

Setting

RF1-RF2

D6

D5

D4

D3

D2

D1

D0

L

L

L

L

L

L

L

Reference I.L.

L

L

L

L

L

L

H

0.25 dB

L

L

L

L

L

H

L

0.5 dB

L

L

L

L

H

L

L

1 dB

L

L

L

H

L

L

L

2 dB

L

L

H

L

L

L

L

4 dB

L

H

L

L

L

L

L

8 dB

H

L

L

L

L

L

L

16 dB

H

H

H

H

H

H

H

31.75 dB

Address Word

Address

Setting

A7

(MSB)

A6

A5

A4

A3

A2

A1

A0

X

X

X

X

X

L

L

L

000

X

X

X

X

X

L

L

H

001

X

X

X

X

X

L

H

L

010

X

X

X

X

X

L

H

H

011

X

X

X

X

X

H

L

L

100

X

X

X

X

X

H

L

H

101

X

X

X

X

X

H

H

L

110

X

X

X

X

X

H

H

H

111

Table 8. Address Word Truth Table

Attenuation Word

D7

D6

D5

D4

D3

D2

D1

D0

(LSB)

X

L

L

L

L

L

L

L

Reference I.L.

X

L

L

L

L

L

L

H

0.25 dB

X

L

L

L

L

H

L

L

1 dB

X

L

L

L

H

L

L

L

2 dB

X

L

L

H

L

L

L

L

4 dB

X

L

H

L

L

L

L

L

8 dB

X

H

L

L

L

L

L

L

16 dB

X

H

H

H

H

H

H

H

31.75 dB

Attenuation

Setting

RF1-RF2

X

L

L

L

L

L

H

L

0.5 dB

Table 9. Attenuation Word Truth Table

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