AD7997 datasheet(29/32 Pages) AD

29 / 32 page

AD7997/AD7998

Rev. 0 | Page 29 of 32

MODE 2 – COMMAND MODE

This mode allows a conversion to be automatically initiated any

time a write operation occurs. In order to use this mode, the

Command Bits C4 to C1 in the address pointer byte shown in

Table 7 must be programmed.

To select a single analog input for conversion in this mode, the

user must set Bits C4 to C1 of the address pointer byte to

indicate which channel to convert on (see Table 26). When all

four command bits are 0, this mode is not in use.

To select a sequence of channels for conversion in this mode,

first select the channels to be included in the sequence by

setting the channel bits in the configuration register. Next, set

the command bits in the address pointer byte to 0111. With the

command bits of the address pointer byte set to 0111, the ADC

knows to look in the configuration register for the sequence of

channels to be converted. The ADC starts converting on the

lowest channel in the sequence and then the next lowest until all

the channels in the sequence are converted. The ADC stops

converting the sequence when it receives a STOP bit.

Figure 29 illustrates a 2-byte read operation from the

conversion result register. This operation is preceded typically

by a write to the address pointer register so that the following

read accesses the desired register, in this case the conversion

result register (see Figure 26). If Command Bits C4 to C1 are set

when the contents of the address pointer register are being

loaded, the AD7997/AD7998 begins to power up and convert

upon the selected channel(s). Power-up begins on the fifth SCL

falling edge of the address point byte, (see point A in Figure 33).

Table 26 shows the channel selection in this mode via

Command Bits C4 to C1 in the address pointer register. The

wake-up, acquisition, and conversion times combined should

take approximately 3 µs. Following the write operation, the

AD7997/AD7998 must be addressed again to indicate that a

read operation is required. The read then takes place from the

conversion result register. This read accesses the conversion

result from the channel selected via the command bits. If

Command Bits C4 to C1 were set to 0111, and Bits D4 and D5

were set in the configuration register, a 4-byte read would be

necessary. The first read accesses the data from the conversion

on VIN1. While this read takes place, a conversion occurs on

VIN2. The second read accesses this data from VIN2. Figure 34

illustrates how this mode operates; the user would first have

written to the configuration register to select the sequence of

channels to be converted before write addressing the part with

the command bits set to 0111.

When operating the AD7997-1/AD7998-1 in Mode 2 with a

high speed mode, 3.4 MHz SCL, the conversion may not be

complete before the master tries to read the conversion result.

If this is the case, the AD7997-1/AD7998-1 holds the SCL line

low during the ACK clock after the read address, until the con-

version is complete. When the conversion is complete, the

AD7997-1/AD7998-1 releases the SCL line and the master can

then read the conversion result.

After the conversion is initiated by setting the command bits

in the address pointer byte, if the AD7997/AD7998 receives a

STOP or NACK from the master, the AD7997/AD7998 stops

converting.

Table 26. Address Pointer Byte

Mode 2, Convert On

Comments

Not selected

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VIN8

Sequence of channels selected in the

configuration register, Bits D11 to D4.

With the pointer Bits P3–P0 set to all 0s,

the next read accesses the results of the

conversion result register.

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