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STNRGPF02 Datasheet(PDF) 16 Page - STMicroelectronics |
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STNRGPF02 Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 43 page ![]() • The device will enter in Burst Mode regulation. The PFC output voltage will oscillate between two settable levels (Vburst_min and Vburst_max). These levels can be defined during device customization. Figure 18. Running mode or Burst mode Time Vout PFC Soft Power-On Vout_ref Vin_pk PFC_OK TSTART PFC Running Mode PFC Burst Mode Vburst_min Vburst_max PFC_OK (a) (b) As soon as the PFC_OK pin becomes low two conditions may occur: The load is applied. a) The device immediately will regulate the output voltage at Vout_ref value. Figure 18 (a) b) The PFC remains in no-load condition: the output voltage will range between Vburst_min and Vburst_max until the load will be applied Figure 18 (b) 3.7.3 Fan control The device offers the possibility to realize a control on cooling system. The customer will defines the power level for the function activation. Pin 20 , FAN gives a CMOS/TTL signal that became low for power level higher than the specified threshold. See Figure 19. STNRGPF02, STNRGPF12 Start-up & Inrush Current Limiter function DS12895 - Rev 2 page 16/43 |
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