PIC16F15213 datasheet(69/439 Pages) MICROCHIP

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Figure 10-3. Reset Start-Up Sequence

Filename:

Reset Start-up Sequence.vsdx

Title:

Last Edit:

1/7/2020

First Used:

Notes:

Rev. Res et S tar

1/7/2020

Note 1:

Code execution begins 10 FOSC cycles after the FOSC clock is released.

VDD

Internal POR

Internal RESET

MCLR

FOSC

Begin Execution

Ext. Clock (EC)

Power-up Timer

code execution

(1)

External Clock (EC modes), PWRTS

code execution

(1)

External Clock (EC modes), PWRTS =

TPWRT

Int. Oscillator

code execution

(1)

Internal Oscillator, PWRTS =

code execution

(1)

Internal Oscillator, PWRTS

TPWRT

VDD

Internal POR

Internal RESET

MCLR

FOSC

Begin Execution

Power-up Timer

Note:

Code execution begins 10 FOSC cycles after the FOSC clock is released.

10.9

Memory Execution Violation

A memory execution violation Reset occurs if executing an instruction being fetched from outside the valid execution

area. The invalid execution areas are:

Addresses outside implemented program memory. Refer to the “Memory Organization” chapter for details

about available Flash size.

Storage Area Flash (SAF) inside program memory, if enabled.

When a memory execution violation is generated, the device is reset and the MEMV bit is cleared to signal the cause

of the Reset. The MEMV bit must be set in the user code after a memory execution violation Reset has occurred to

detect further violation Resets.

10.10 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS, PCON0 and PCON1 registers are updated to indicate the cause of the

Reset. The following tables show the Reset conditions of these registers.

Table 10-3. Reset Status Bits and Their Significance

STKOVF STKUNF RWDT RMCLR

POR

BOR

MEMV

Condition

Power-on Reset

Illegal, TO is set on

POR

Illegal, PD is set on

POR

PIC16F15213/14/23/24/43/44

Resets

and its subsidiaries

Data Sheet

DS40002195E-page 69

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