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STM32H7B0AB Datasheet(PDF) 2 Page - STMicroelectronics |
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STM32H7B0AB Datasheet(HTML) 2 Page - STMicroelectronics |
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2 / 205 page  Reset and power management • 2 separate power domains, which can be independently clock gated to maximize power efficiency: – CPU domain (CD) for Arm® Cortex® core and its peripherals, which can be independently switched in Retention mode – Smart run domain (SRD) for reset and clock control, power management and some peripherals • 1.62 to 3.6 V application supply and I/Os • POR, PDR, PVD and BOR • Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs • Dedicated SDMMC power supply • High power efficiency SMPS step-down converter regulator to directly supply VCORE or an external circuitry • Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry • Voltage scaling in Run and Stop mode • Backup regulator (~0.9 V) • Low-power modes: Sleep, Stop and Standby • VBAT battery operating mode with charging capability • CPU and domain power state monitoring pins Interconnect matrix • 3 bus matrices (1 AXI and 2 AHB) • Bridges (5× AHB2APB, 3× AXI2AHB) 5 DMA controllers to unload the CPU • 1× high-speed general-purpose master direct memory access controller (MDMA) • 2× dual-port DMAs with FIFO and request router capabilities • 1× basic DMA with request router capabilities • 1x basic DMA dedicated to DFSDM Up to 35 communication peripherals • 4× I2C FM+ interfaces (SMBus/PMBus) • 5× USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART • 6× SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock and 1 x SPI/I2S in LP domain (up to 125 MHz) • 2x SAIs (serial audio interface) • SPDIFRX interface • SWPMI single-wire protocol master interface • MDIO Slave interface • 2× SD/SDIO/MMC interfaces (up to 133 MHz) • 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) • 1× USB OTG interfaces (1HS/FS) • HDMI-CEC • 8- to 14-bit camera interface up to 80 MHz • 8-/16-bit parallel synchronous data input/output slave interface (PSSI) 11 analog peripherals • 2× ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS) • 1× analog and 1x digital temperature sensors • 1× 12-bit single-channel DAC (in SRD domain) + 1× 12-bit dual-channel DAC • 2× ultra-low-power comparators • 2× operational amplifiers (8 MHz bandwidth) • 2× digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters and 1x in SRD domain with 2 channels/1 filter STM32H7B0xB DS13196 - Rev 7 page 2/205 |
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