MP2176 – 6V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2176 Rev. 1.0

www.MonolithicPower.com

17

4/17/2018

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© 2018 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage with Large ESR

Capacitors

For applications that use electrolytic capacitors

or POSCAPs with a controlled ERS output as

output capacitors, the output voltage is set by

feedback resistors R1 and R2 (see Figure 7).

R1

R2

ESR

POSCAP

SW

Vo

L

FB

Figure 7: Simplified POSCAP Circuit

First, choose a value for R2. R2 should be

chosen reasonably, since a small R2 leads to

considerable quiescent current loss, but a large

R2 makes FB noise-sensitive. R2 should be

between 5 - 100

kΩ. Use a comparatively larger

R2 when VOUT is low and a smaller R2 when

VOUT is high. Considering the output ripple,

determine R1 with Equation (13):

OUT

OUT

REF

12

REF

1

V

V

V

2

RR

V

  





(13)

Where ∆VOUT is the output ripple determined in

Equation (22).

Setting the Output Voltage with Small ESR

Capacitors

When low ESR ceramic capacitors are used in

the output, an external voltage ramp should be

added to FB through a resistor (R4) and

capacitor (C4). The output voltage is influenced

by the ramp voltage (VRAMP) in addition to a

resistor divider (see Figure 8).

R1

R2

Ceramic

SW

FB

Vo

L

R9

R4

C4

Figure 8: Simplified Ceramic Capacitor Circuit

VRAMP can be calculated with Equation (6). R2

should be chosen reasonably, since a small R2

leads to considerable quiescent current loss,

but a large R2 makes FB noise-sensitive. R2

should

be

between

5

-

100

kΩ. Use a

comparatively larger R2 when VOUT is low and a

smaller R2 when VOUT is high. Then the value of

R1 can be determined with Equation (14):

2

1

FB( AVG)

2

OUT

FB( AVG)

4

9

R

R

V

R

V

V

R

R







(14)

Where VFB(AVG) is the average value on FB. The

value of VFB(AVG) varies with VIN, VOUT, and the

load condition, meaning the load regulation is

strictly related to VFB(AVG). The line regulation is

related to VFB(AVG), as well. For better load or

line regulation, use a lower VRAMP once it meets

Equation (8).

For PWM operation, VFB(AVG) can be calculated

with Equation (15):

12

FB(AVG)

REF

RAMP

1

2

9

R // R

1

V

V

V

2

R // R

R



 





(15)

Usually, R9 is set to 0Ω. R9 should be five

times smaller than R1//R2 to minimize its

influence on Vramp. To achieve better noise

immunity, R9 can also be set using Equation

(16):

12

9

12

RR

1

R

10

R

R







(16)

Using Equation (14) and Equation (15) to

calculate the output voltage can be complicated.

To simplify the calculation of R1 in Equation

(14), add a DC-blocking capacitor (Cdc) to filter

the DC influence from R4 and R9. Figure 9

shows a simplified circuit with external ramp

compensation and a Cdc. With this capacitor,

R1 can calculated easily for PWM mode

operation with Equation (17):

OUT

REF

RAMP

12

REF

RAMP

1

V

V

V

2

RR

1

VV

2



 





(17)