MP2176 – 6V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2176 Rev. 1.0

www.MonolithicPower.com

18

4/17/2018

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© 2018 MPS. All Rights Reserved.

Cdc is suggested to be at least 10 times larger

than C4 for better DC blocking performance.

Cdc

should

be

no

larger

than

0.47

μF,

considering the start-up performance. For better

FB noise immunity, combine a larger Cdc with a

reduced R1 and R2 to limit the Cdc to a

reasonable value without affecting system start-

up. Note that even when the Cdc is applied, the

load and line regulation are still related to VRAMP.

R1

R2

Ceramic

SW

FB

Vo

L

Cdc

R4

C4

Figure 9: Simplified Circuit of a Ceramic

Capacitor with a DC Blocking Capacitor

Selecting the Input Capacitor

The input current to the step-down converter is

discontinuous

and

therefore

requires

a

capacitor to supply AC current to the step-down

converter

while

maintaining

the

DC

input

voltage. Ceramic capacitors are recommended

for the best performance. In the layout, place

the input capacitors as close to IN as possible.

The capacitance varies significantly with the

temperature. Capacitors with X5R and X7R

ceramic dielectrics are recommended because

they are fairly stable over-temperature.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated with Equation (18):

OUT

OUT

CIN

OUT

IN

IN

VV

I

I

(1

)

VV





 

(18)

The worst-case condition occurs at VIN = 2VOUT,

shown in Equation (19):

OUT

CIN

I

I

2



(19)

For simplification, choose an input capacitor

with an RMS current rating greater than half of

the maximum load current.

The input capacitance value determines the

input voltage ripple of the converter. If there is

an input voltage ripple requirement in the

system design, choose an input capacitor that

meets the specification The input voltage ripple

can be estimated with Equation (20):

OUT

OUT

OUT

IN

SW

IN

IN

IN

I

V

V

V

(1

)

f

C

V

V







 



(20)

The worst-case condition occurs at VIN = 2VOUT,

shown in Equation (21):

OUT

IN

SW

IN

I

1

V

4

f

C



 



(21)

Selecting the Output Capacitor

The output capacitor is required to maintain the

DC

output

voltage.

Ceramic

or

POSCAP

capacitors

are

recommended.

The

output

voltage ripple can be estimated with Equation

(22):

OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V

(1

) (R

)

f

L

V

8 f

C





 











(22)

In

the

case

of

ceramic

capacitors,

the

impedance

at

the

switching

frequency

is

dominated by the capacitance. The output

voltage

ripple

is

caused

mainly

by

the

capacitance.

For

simplification,

the

output

voltage ripple can be estimated with Equation

(23):

OUT

OUT

OUT

2

IN

SW

OUT

VV

V

(1

)

V

8 f

L C





 



 

(23)

The output voltage ripple caused by the ESR is

very small and therefore requires an external

ramp to stabilize the system. The external ramp

can be generated through a resistor (R4) and

capacitor (C4) following Equation (4), Equation

(7), and Equation (8).

In the case of POSCAP capacitors, the ESR

dominates the impedance at the switching

frequency. The ramp voltage generated from

the ESR is high enough to stabilize the system

and therefore does not require an external ramp.

A

minimum

ESR

value

(calculated

with

Equation (3)) is required to ensure stable

operation of the converter.