MP2176 – 6V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2176 Rev. 1.0

www.MonolithicPower.com

21

4/17/2018

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PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation.

A

four-layer

layout

is

strongly

recommended

to

achieve

better

thermal

performance. For best results, refer to Figure

10 and Figure 11 and follow the guidelines

below.

1. Place

at

least

nine

vias

(10/20mil

hole/diameter size) just beneath the IC for

the best decoupling effect.

2. Place

10

or

more

vias

(10/25mil

hole/diameter size) each for the input and

GND copper next to IN and PGND to

improve the thermal performance.

3. Place a 22µF (1206/1210) input capacitor

(C1B) on the bottom layer just beneath the

VIN and PGND vias for the best input

decoupling effect.

4. If VIN/PGND vias are not allowed beneath

the IC: Place a 22µF input capacitor with a

1206/1210 package (C1C) is required on

the top layer, connecting to the VIN and

PGND copper directly (within 2mm of the IC

edge).

5. Place a solid PGND layer on the first inner

layer just below the IC layer.

6. Keep the high-current paths (GND, IN, and

SW) very close to the device with short,

direct, and wide traces.

7. Place the VCC decoupling capacitor (C5) as

close to VCC as possible.

8. Connect the VCC GND net to the PGND

copper.

9. Connect all AGND signals together to

AGND.

10. Kelvin-connect AGND to PGND near the C5

GND pad on the top layer.

11. Keep the AGND trace 20mil or wider.

12. Place the external feedback resistors next

to FB.

13. Ensure that there is no via on the FB trace.

14. Keep the vias away from the switching node

(SW).

15. Keep the BST voltage path (BST, C3, RBST,

and SW) as short as possible.

16. Keep the VOUT sense trace away from noise

signals (SW, VIN, etc).

17. Place the VOUT sense point at a stable, quiet

output point close to the VOUT capacitor.

MP2176

C1

C3

RBST

C2

C4

R4

R1

R2

VOUT

L1

RFREQ

VIN

IN

FREQ

BST

SW

FB

VCC

PG

VCC

PG

R3

C5

EN

EN

SS

C6

PGND

AGND

Figure 10: Schematic for PCB Layout Guidelines

R3

FREQ

IN

R3

C1B

R3

R1

R3

R2

R3

R4

R3

C4

L1

R3

C2

SW

SW

FREQ

IN

GND

GND

VIN

GND

SW

VOUT

C3

GND

R3

C5

BST

<2mm

C1C

<2mm

VIN

PGND

Figure 11: Recommended Layout