MP2176 – 6V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2176 Rev. 1.0

www.MonolithicPower.com

14

4/17/2018

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© 2018 MPS. All Rights Reserved.

Figure 3: Jitter in PWM Mode

Ramp with Large ESR Capacitor

When POSCAPs or other types of capacitors

with large ESR are applied as output capacitors,

the ESR ripple dominates the output ripple, and

the slope on FB is related to the ESR. Figure 4

shows an equivalent circuit in PWM mode with

the HS-FET off and without an external ramp

circuit. Refer to the Application Information

section on page 17 for design steps using large

ESR capacitors.

R1

R2

ESR

POSCAP

SW

Vo

L

FB

Figure 4: Simplified Circuit in PWM Mode without

External Ramp Compensation

To achieve stability when no external ramp is

applied, calculate the ESR value with Equation

(3):

SW

ON

ESR

OUT

tt

0.7

2

R

C







(3)

Where TSW is the switching period.

Ramp with Small ESR Capacitor

When the output capacitors are ceramic, the

ESR ripple is not high enough to stabilize the

system, and external ramp compensation is

required. Refer to the Application Information

section on page 17 for design steps using small

ESR capacitors.

R1

R2

Ceramic

SW

FB

Vo

L

R4

C4

IR4

IC4

IFB

R9

Figure 5: Simplified Circuit in PWM Mode with

External Ramp Compensation

Figure 5 shows a simplified equivalent circuit

with the HS-FET off and using an external ramp

compensation circuit (R4, C4) in PWM mode.

The external ramp is derived from the inductor

ripple current. Calculate C4, R9, R1, and R2

with Equation (4):

12

9

SW

4

1

2

RR

11

R

2

f

C

20

R

R













 







(4)

The current of R4 can be calculated with

Equation (5):

R4

C4

FB

C4

I

I

I

I







(5)

The ramp on VFB can then be estimated with

Equation (6):

IN

O

12

RAMP

ON

4

4

1

2

9

VV

R // R

Vt

R

C

R // R

R









 





(6)

The downward slope of the VFB ripple can then

be calculated with Equation (7):

OUT

RAMP

SLOPE1

off

4

4

V

V

V

t

R

C







(7)

As shown in Equation (7), if there is instability in

PWM mode, either R4 or C4 can be reduced. If

C4 cannot be reduced further due to limitations

from Equation (4), then only R4 can be reduced.

For stable PWM operation, Vslope1 should be

designed following Equation (8):

SW

ON

3

ESR

OUT

O

SLOPE1

OUT

OUT

sw

on

tt

RC

0.7 I

10

0.7

2

VV

2 L C

t

t





















 



(8)

Where IO is the load current.