HD4046212RFS datasheet(23/157 Pages) RENESAS

23 / 157 page

HD404629R Series

Item

Abbr.

Status After Cancel-

lation of Stop Mode by

STOPC Input

Status After Cancel-

lation of Stop Mode by

RESET Input

Status After all Other Types

of Reset

Carry flag

(CA)

Pre-stop-mode values are not guaranteed;

Pre-MCU-reset values

Accumulator

(A)

values must be initialized by program

are not guaranteed; val-

B register

(B)

ues must be initialized by

W register

(W)

program

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register

(SRL, SRU)

RAM

Pre-stop-mode values are retained

RAM enable flag

(RAME)

Port mode

(PMRC2)

Pre-stop-mode

values are retained

System clock

select register bit 3

(SSR3)

Interrupts

The MCU has 11 interrupt sources: five external signals (

INT

0, INT1, INT2–INT4), four timer/ counters

(timers A, B, C, and D), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt

source, and an interrupt enable flag (IE) controls the entire interrupt process.

Some vector addresses are shared by two different interrupts. They are timer B and INT

2, timer C and

INT

3, timer D and INT4, and A/D converter and serial interface interrupts.

So the type of request that has

occurred must be checked at the beginning of interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are

reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag

(IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector

addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in

table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the

interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to

that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in

figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The

IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack

HD4046212RFS Datasheet(PDF) 23 Page - Renesas Technology Corp

HD4046212RFS Datasheet(HTML) 23 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL