TIMING SOLUTIONS

7

MOTOROLA

APPLICATIONS INFORMATION

Programming the MPC9600

The MPC9600 clock driver outputs can be configured into

several divider modes. Additionally the external feedback of

the device allows for flexibility in establishing various input to

output frequency relationships. The selectable feedback

divider of the three output groups allows the user to configure

the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency

ratios. The use of even dividers ensure that the output duty

cycle is always 50%. Table 6 illustrates the various output

configurations, the table describes the outputs using the

input clock frequency CLK as a reference.

The feedback divider division settings establish the output

relationship, in addition, it must be ensured that the VCO will

be stable given the frequency of the outputs desired. The

feedback frequency should be used to situate the VCO into a

frequency range in which the PLL will be stable. The design

of the PLL supports output frequencies from 50 MHz to 200

MHz while the VCO frequency range is specified from 200

MHz to 400 MHz and should not be exceeded for stable

operation.

Table 6: Output Frequency Relationshipa for QFB connected to FB_IN

Configuration Inputs

Input

Frequency

Output Frequency Ratio and Range

FSEL_FB

FSELA

FSELB

FSELC

Range CLK

[MHz]

Ratio, QAx [MHz]

Ratio, QBx [MHz]

Ratio, QCx [MHz]

0

0

0

0

4

SCLK (100–200)

4

SCLK (100–200)

4

SCLK (100–200)

0

0

0

1

4

SCLK (100–200)

4

SCLK (100–200)

2

SCLK (50.0–100)

0

0

1

0

4

SCLK (100–200)

2

SCLK (50.0–100)

4

SCLK (100–200)

0

0

1

1

25.0–50.0

4

SCLK (100–200)

2

SCLK (50.0–100) 2SCLK (50.0–100)

0

1

0

0

2

SCLK (50.0–100)

4

SCLK (100–200)

4

SCLK (100–200)

0

1

0

1

2

SCLK (50.0–100)

4

SCLK (100–200)

2

SCLK (50.0–100)

0

1

1

0

2

SCLK (50.0–100) 2SCLK (50.0–100)

4

SCLK (100–200)

0

1

1

1

2

SCLK (50.0–100) 2SCLK (50.0–100) 2SCLK (50.0–100)

1

0

0

0

6

SCLK (100–200)

6

SCLK (100–200)

6

SCLK (100–200)

1

0

0

1

6

SCLK (100–200)

6

SCLK (100–200)

3

SCLK (50.0–100)

1

0

1

0

6

SCLK (100–200)

3

SCLK (50.0–100)

6

SCLK (100–200)

1

0

1

1

16.67–33.33

6

SCLK (100–200)

3

SCLK (50.0–100) 3SCLK (50.0–100)

1

1

0

0

3

SCLK (50.0–100)

6

SCLK (100–200)

6

SCLK (100–200)

1

1

0

1

3

SCLK (50.0–100)

6

SCLK (100–200)

3

SCLK (50.0–100)

1

1

1

0

3

SCLK (50.0–100) 3SCLK (50.0–100)

6

SCLK (100–200)

1

1

1

1

3

SCLK (50.0–100) 3SCLK (50.0–100) 3SCLK (50.0–100)

a. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400.

Typical and Maximum Period Jitter Specification

Device Configuration

QA0 to QA6

QB0 to QB6

QC0 to QC6

Typ

Max

Typ

Max

Typ

Max

All output banks in

B2 or B4 divider configurationa

B2 (FSELA=0 and FESLB=0 and FSELC=0)

B4 (FSELA=1 and FESLB=1 and FSELC=1)

25

20

50

70

50

50

70

100

25

20

50

70

Mixed

B2/B4 divider configurationsb

for output banks in

B2 divider configurations

for output banks in

B4 divider configurations

80

25

130

70

100

60

150

100

80

25

130

70

a. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 1 for an example configuration.

b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. See Figure 2 for an example.

Typical and Maximum Cycle–to–cycle Jitter Specification

Device Configuration

QA0 to QA6

QB0 to QB6

QC0 to QC6

Typ

Max

Typ

Max

Typ

Max

All output banks in

B2 or B4 divider configurationa

B2 (FSELA=0 and FESLB=0 and FSELC=0)

B4 (FSELA=1 and FESLB=1 and FSELC=1)

40

40

90

110

80

120

130

180

40

40

90

110

Mixed

B2/B4 divider configurationsb

for output banks in

B2 divider configurations

for output banks in

B4 divider configurations

150

30

250

110

200

120

280

180

150

30

250

110

a. In this configuration, all MPC9600 outputs generate the same clock frequency.

b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately.

Freescale Semiconductor, Inc.

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