MPC9600FA datasheet(9/16 Pages) FREESCALE

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TIMING SOLUTIONS

MOTOROLA

Using the MPC9600 in zero–delay applications

Nested clock trees are typical applications for the

MPC9600. For these applications the MPC9600 offers a

differential LVPECL clock input pair as a PLL reference. This

allows for the use of differential LVPECL primary clock

distribution devices such as the Motorola MC100ES6111 or

MC100ES6226, taking advantage of its superior low-skew

performance. Clock trees using LVPECL for clock distribution

and the MPC9600 as LVCMOS PLL fanout buffer with zero

insertion delay will show significantly lower clock skew than

clock distributions developed from CMOS fanout buffers.

The external feedback option of the MPC9600 PLL allows

for its use as a zero delay buffer. The PLL aligns the feedback

clock output edge with the clock input reference edge and

virtually eliminates the propagation delay through the device.

The remaining insertion delay (skew error) of the

MPC9600 in zero-delay applications is measured between

the reference clock input and any output. This effective delay

consists of the static phase offset (SPO or t(

∅)), I/O jitter

(tJIT(

∅), phase or long-term jitter), feedback path delay and

the output-to-output skew (tSK(O) relative to the feedback

output.

Calculation of part-to-part skew

The MPC9600 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs (CCLK or

PCLK) of two or more MPC9600 are connected together, the

maximum overall timing uncertainty from the common CCLK

input to any output is:

tSK(PP) = t(

∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) CF

This maximum timing uncertainty consist of 4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

Figure 6. MPC9600 max. device-to-device skew

tPD,LINE(FB)

tJIT(

∅)

+tSK(O)

–t(

∅)

+t(

∅)

tJIT(

∅)

+tSK(O)

tSK(PP)

Max. skew

TCLKCommon

QFBDevice 1

Any QDevice 1

QFBDevice2

Any QDevice 2

Due to the statistical nature of I/O jitter a RMS value (1

is specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

Table 8: Confidence Facter CF

Probability of clock edge within the distribution

± 1s

0.68268948

± 2s

0.95449988

± 3s

0.99730007

± 4s

0.99993663

± 5s

0.99999943

± 6s

0.99999999

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation a

I/O jitter confidence factor of 99.7% (

± 3s) is assumed,

resulting in a worst case timing uncertainty from input to any

output of -261 ps to 341 ps relative to CCLK (VCC=3.3V and

fVCO = 200 MHz):

tSK(PP) =

[–60ps...140ps] + [–150ps...150ps] +

[(17ps

@ –3)...(17ps @ 3)] + tPD, LINE(FB)

tSK(PP) =

[–261ps...341ps] + tPD, LINE(FB)

Above equation uses the maximum I/O jitter number

shown in the AC characteristic table for VCC=3.3V (17 ps

RMS). I/O jitter is frequency dependant with a maximum at

the lowest VCO frequency (200 MHz for the MPC9600).

Applications using a higher VCO frequency exhibit less I/O

jitter than the AC characteristic limit. The I/O jitter

characteristics in Figure 7. can be used to derive a smaller

I/O jitter number at the specific VCO frequency, resulting in

tighter timing limits in zero-delay mode and for part-to-part

skew tSK(PP).

Figure 7. Max. I/O Jitter versus VCO frequency for

VCC=2.5V and VCC=3.3V

Driving Transmission Lines

The MPC9600 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Motorola application note

AN1091. In most high performance clock networks

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme either series terminated or parallel

Freescale Semiconductor, Inc.

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