ACPL datasheet(8/10 Pages) AVAGO

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Switching Specifications (AC)

-40°C ≤ TA ≤ 100°C, 4.5V ≤ VCC ≤ 20V, 6mA ≤ IF(ON) ≤ 10 mA, 0V ≤ VF(OFF) ≤ 0.8V.

All Typicals at TA = 25°C, IF(ON) = 6 mA unless otherwise specified.

Parameter

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Fig.

Note

Propagation Delay Time

to Logic Low Output

Leve

tPHL

150

350

With Peaking Capacitor

5,6

Propagation Delay Time

to Logic High Output

Level

tPLH

110

350

With Peaking Capacitor

5,6

Pulse Width Distortion

PWD

250

| tPHL - tPLH |

Propagation Delay Dif-

ference Between Any 2

Parts

PDD

-100

250

Output Rise Time (10-

90%)

5,8

Output Fall Time (90-

10%)

5,8

Logic High Common

Mode Transient Immu-

nity

|CMH|

-30000

V/µs

|VCM| = 1000 V, IF = 6.0 mA,

VCC = 5 V, TA = 25 C

Logic Low Common

Mode Transient Immu-

nity

|CML|

30000

V/µs

|VCM| = 1000 V, VF = 0 V, VCC

= 5 V, TA = 25 C

Package Characteristics

* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage

rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level

safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.

Notes:

1. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.

2. Duration of output short circuit time should not exceed 10 ms.

3. Input capacitance is measured between pin 2 and pin 3.

4. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.

5. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the

output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing

edge of the output pulse.

6. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V. CML

is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V.

7. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage detec-

tion current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN

60747-5-2 Insulation Characteristics Table, if applicable.

8. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device.

9. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended.

10. The difference between tPLH and tPHL between any two devices under the same test condition.

Parameter

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Fig.

Note

Input-Output Momentary

Withstand Voltage*

VISO

3750

Vrms

RH < 50%, t = 1 min.TA

= 25°C

4,7

Input-Output Resistance

RI-O

1012

VI-O = 500 Vdc

Input-Output Capacitance

CI-O

0.6

f = 1 MHz, VI-O = 0 Vdc

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