CCG3PA datasheet(6/37 Pages) CYPRESS

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Document Number: 002-16951 Rev. *F

Page 6 of 37

EZ-PD™ CCG3PA Datasheet

Power Systems Overview

CCG3PA can operate from two possible external supply sources:

VBUS_IN_DISCHARGE (3.0 V–24.5 V) or VDDD (2.7 V–5.5 V).

When powered through VBUS_IN_DISCHARGE, the internal

regulator generates VDDD of 3.3 V for chip operation. The

regulated supply, VDDD, is either used directly inside some

analog blocks or further regulated down to VCCD (1.8 V), which

powers majority of the core using the regulators. CCG3PA has

three different power modes: Active, Sleep, and Deep Sleep.

Transitions between these power modes are managed by the

power

system.

When

powered

through

the

VBUS_IN_DISCHARGE pin, VDDD cannot be used to power

external devices and should be connected to a 1-µF capacitor for

the regulator stability only. These pins are not supported as

power supplies. Refer to the application diagrams for capacitor

connections.

Figure 1. Power System Requirement Block Diagram

Table 1. CCG3PA Power Modes

Mode

Description

Power-On Reset (POR)

Power is valid and an internal reset source is asserted or SleepController is sequencing the system

out of reset.

ACTIVE

Power is valid and CPU is executing instructions.

SLEEP

Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated to

save power.

DEEP SLEEP

Main regulator and most blocks are shut off. DeepSleep regulator powers logic, but only

low-frequency clock is available.

VSS

VBUS_IN_DISCHARGE

VDDD

1.8-V

Regulator

VCCD

Core

GPIO

Tx/Rx

CCG3PA

CC1, CC2

VSS

SHV

Regulator

UV/

OVP

Gate Driver

VBUS_P_CTRL

Gate Driver

VBUS_C_CTRL

VBUS_C_MON

_DISCHARGE

1uF

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