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Block diagram:

The block diagram is shown in fig.3. The IC consists of a spinning Hall probe (monocell

in the centre of the chip) with a chopped preamplifier. Next there is a summing node for

threshold level adjustment. The threshold switching is actually done in the main

comparator at a signal level of „0“. This means, that the whole signal is shifted by this

summing node in that way, that the desired switching level occurs at zero. This adjusted

signal is fed into an A/D-converter. The converter feeds a digital calibration logic. This

logic monitors the digitised signal by looking for minimum and maximum values and also

calculates correction values for threshold adjustment. The static switching level is simply

done by fetching a digital value out of a PROM. The dynamic switching level is done by

calculating a weighted average of min and max value. For example, a factor of

approximately 71% can be achieved by doubling the weight of the max value. Generally

Serial interface:

The serial interface is used to program the chip. At the same time it can be used to

provide special settings and to read out several internal registers status bits. The

interface description consists of a physical layer and a logical layer. The physical layer

describes format, timing and voltage information, whereas the logical layer describes the

available commands and the meaning of bits, words and addresses.

Physical interface layer:

The data transmission is done over the VS-pin, which generates input information and

clock timing, and the out-pin Q, which delivers the output data. Generally the interface

function is disabled; this means, that in normal operation including normal supply

distortion the interface is not active and therefore the chip operates in its normal way. A

special initialisation sequence must be performed to enter the interface mode that is also

referred to as “testmode”. There are two possible ways to achieve the testmode. They

are called OpenPowerOn and OpenSyncVDD. For already programmed devices this

initialisation procedures to testmode are not possible. The IC is still in test mode after

programming the IC. It is possible to read out the programmed values as long as you do

not leave the test mode.

OpenPowerOn: For a short time after power on or reset the chip monitors the output

signal. The internal logic brings the output into a high impedance state, which will be a

logical “high” caused by the external pull-up resistor. If now the chip sees a logical “low”

(for at least 1ms), which is an output voltage lower than 0.3V, the chip enters the

testmode.

Data transmission: Serial transmission is done in words (LSB first). A logical „1“ is

represented by a long (2/3 of one period) „high“ voltage level (higher than 5V) on the

supply followed by a short (1/3 of one period) „low“ voltage level (lower than 5V),

whereas a logical „0“ is represented by a short „high“ level on the supply followed by a

long „low“ level. At the same time this high/low voltage combination, which forms in fact

a bit, acts as a serial interface clock which clocks out logical high / low values on the

output. Due to the increased capacity a clocking period of 200µs is recommended

(standard value for 4.7nF capacitor: 100µs).