M95M02-DF datasheet(25/45 Pages) STMICROELECTRONICS

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6.10

Lock ID

The lock ID instruction permanently locks the identification page in read-only mode. Before this instruction can be

accepted, a write enable (WREN) instruction must have been executed.

The lock ID instruction is issued by driving chip select (S) low, sending the instruction code, the address and a

data byte on serial data input (D), and driving chip select (S) high. In the address sent, A10 must be equal to 1,

all other address bits are "Don't Care". The data byte sent must be equal to the binary value xxxx xx1x, where x =

Don't Care.

Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data

byte, and before the next rising edge of serial clock (C). Otherwise, the lock ID instruction is not executed.

Driving chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration

is tW (as specified in AC characteristics in Section 9 DC and AC parameters). The instruction sequence is shown

in Figure 19.

The instruction is discarded, and is not executed, under the following conditions:

•

If a write cycle is already in progress

•

If block protect bits (BP1, BP0) = (1, 1)

•

If a rising edge on chip select (S) happens outside of a byte boundary

Figure 19. Lock ID sequence

3 4 5 6 7 8 9 10

28 29 30 31 32 33 34 35

22 21

3 2 1 0

36 37 38

High impedance

Instruction

24-bit address

7 6 5 4 3 2

Data byte

M95M02-DR M95M02-DF

Lock ID

DS7024 - Rev 13

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