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PIC18F1XK50 Datasheet(PDF) 68 Page - Microchip Technology |
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PIC18F1XK50 Datasheet(HTML) 68 Page - Microchip Technology |
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68 / 422 page  PIC18F/LF1XK50 DS41350D-page 68 Preliminary 2010 Microchip Technology Inc. FIGURE 7-1: PIC18 INTERRUPT LOGIC TMR0IE GIEH/GIE GIEL/PEIE Wake-up if in Interrupt to CPU Vector to Location 0008h INT2IF INT2IE INT2IP INT1IF INT1IE INT1IP TMR0IF TMR0IE TMR0IP RABIF RABIE RABIP IPEN TMR0IF TMR0IP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP RABIF RABIE RABIP INT0IF INT0IE GIEL/PEIE Interrupt to CPU Vector to Location IPEN IPEN 0018h SSPIF SSPIE SSPIP SSPIF SSPIE SSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts ADIF ADIE ADIP High Priority Interrupt Generation Low Priority Interrupt Generation RCIF RCIE RCIP Additional Peripheral Interrupts Idle or Sleep modes GIEH/GIE Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable. (1) (1) |
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