PIC18F1XK50 datasheet(85/422 Pages) MICROCHIP

85 / 422 page

 2010 Microchip Technology Inc.

Preliminary

DS41350D-page 85

PIC18F/LF1XK50

PORTA: PORTA REGISTER

U-0

R/W-x

R-x

U-0

R/W-x

—

—RA5

RA4

RA3

—RA1

RA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5-3

RA<5:3>: PORTA I/O Pin bit(1)

1 = Port pin is > VIH

0 = Port pin is < VIL

bit 2

Unimplemented: Read as ‘0’

bit 1-0

RA<1:0>: PORTA I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1:

The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0).

Otherwise, RA3 reads as ‘0’. This bit is read-only.

TRISA: PORTA TRI-STATE REGISTER

U-0

R/W-1

U-0

—

TRISA5

TRISA4

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5-4

TRISA<5:4>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

bit 3-0

Unimplemented: Read as ‘0’

Note 1:

TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

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