9

Atmel LED Driver-MSL3082

Note 1. Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either

SDA or SCL is held low for t

Note 2. t

Note 3. t

Note 4. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state

Note 5. The maximum SDA and SCL rise times are 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be

connected between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time

Note 6. The MSL3082 includes input filters on SDA, SCL, AD0, and AD1 inputs that suppress noise less than 50ns

Note 7. Parameter is guaranteed by design, and is not production tested

Note 8. Subject to thermal dissipation characteristics of the device

Note 9. When mounted according to JEDEC JEP149 and JESD51-12 for a one-layer PCB,

θ

Block Diagram

PARAMETER

CONDITIONS AND NOTES

MIN

TYP

MAX

UNIT

SDA data valid acknowledge time

t

VD:ACK

(Note 2)

0.05

0.55

µs

SDA data valid time

t

VD:DAT

(Note 3)

0.05

0.55

µs

SDA data set-up time

t

SU:DAT

100

ns

SCL clock low period

t

LOW

0.5

µs

SCL clock high period

t

HIGH

0.26

µs

SDA, SCL fall time

t

F

(Note 4, Note 5)

120

ns

SDA, SCL rise time

t

R

120

ns

SDA, SCL input suppression

filter period

t

SP

(Note 6)

50

ns

Atmel LED Driver-MSL3082

8-string, High-power, White or RGB LED Driver for TV,

Blacklighting, or Intelligent Solid-state Lighting