MPC8315CVRADDA datasheet(48/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

I2C

13.2

I2C AC Electrical Specifications

This table provides the AC timing parameters for the I2C interface.

This figure provides the AC test load for the I2C.

Figure 33. I2C AC Test Load

Table 48. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 47)

Parameter

Symbol 1

Min

Max

Unit

SCL clock frequency

fI2C

400

kHz

Low period of the SCL clock

tI2CL

1.3

—

s

High period of the SCL clock

tI2CH

0.6

—

s

Setup time for a repeated START condition

tI2SVKH

0.6

—

s

Hold time (repeated) START condition (after this period, the first clock pulse is

generated)

tI2SXKL

0.6

—

s

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0 2

—

0.9 3

s

Fall time of both SDA and SCL signals

tI2CF

—

300

Setup time for STOP condition

tI2PVKH

0.6

—

s

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

s

Noise margin at the LOW level for each connected device (including hysteresis)

VNL

0.1

 NVDD

—

Noise margin at the HIGH level for each connected device (including hysteresis)

VNH

0.2

 NVDD

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to

the high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the start

condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH

symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative

to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

2. MPC8315E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

3. The maximum tI2DVKH has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. MPC8315E does not follow the I2C-BUS Specifications version 2.1 regarding the tI2CF AC parameter.

Output

Z0 = 50 

NVDD/2

RL = 50 

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