MPC8315CVRADDA datasheet(67/106 Pages) FREESCALE

67 / 106 page

MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI Express

16.5

Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 51 is specified using the passive compliance/test measurement load (see

Figure 52) in place of any real PCI Express RX component. In general, the minimum receiver eye diagram

measured with the compliance/test measurement load (see Figure 52) is larger than the minimum receiver

eye diagram measured over a range of systems at the input receiver of any real PCI Express component.

The degraded eye diagram at the input Receiver is due to traces internal to the package as well as silicon

parasitic characteristics which cause the real PCI Express component to vary in impedance from the

compliance/test measurement load. The input receiver eye diagram is implementation specific and is not

specified. RX component designer should provide additional margin to adequately compensate for the

degraded minimum Receiver eye diagram (shown in Figure 51) expected at the input receiver based on an

adequate combination of system simulations and the return loss measured looking into the RX package

and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the

eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50

 to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50

 probes—see Figure 52). Note that the series capacitors,

CPEACCTX, are optional for the return loss measurement.

Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification

16.5.1

Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within

0.2 inches of the package pins, into a test/measurement load shown in Figure 52.

VRX-DIFFp-p-MIN > 175 mV

0.4 UI = TRX-EYE-MIN

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

MPC8315CVRADDA Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc