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80960KA Datasheet(PDF) 40 Page - Intel Corporation |
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80960KA Datasheet(HTML) 40 Page - Intel Corporation |
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40 / 43 page ![]() 80960KA 37 Figure 31. Interrupt Acknowledge Transaction CLK2 TX TX Ta Td Tr Tr TI TI TI TI TI Ta Tw Td INTR LAD31:0 ALE ADS INTA DT/R DEN LOCK READY NOTE: INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1. For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted. INTERRUPT ACKNOWLEDGEMENT CYCLE 1 IDLE (5 BUS STATES) INTERRUPT ACKNOWLEDGEMENT CYCLE 2 PREVIOUS CYCLE ADDR VECTOR ADDR CLK |
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