SRC0 datasheet(24/48 Pages) STMICROELECTRONICS

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Waveforms

SRC0

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DocID026008 Rev 2

Figure 18. Long push (option with RST assertion)

tSRD period is set by external capacitor CSRD.

PB ignored during tINT_Min.

PSHOLD signal is ignored during tON_BLANK. Its level is checked after tON_BLANK expires and if it is high the

EN signal remains asserted, otherwise EN goes low.

Internal pull-down resistor 300 k

 is connected to PS

HOLD input during startup when device is reset.

internal pull-down resistor

connected to PS

HOLD

input

HOLD

ignored

PB status

ignored

tON _BLANK

tSR D

(1)

set by C SR D

V CC undervoltage detection status ignored

HOLD

(3, 4)

INT

(2)

RST

Push-button pressed

and PB connected to

GND

tDEBOUNCE

tREC

Push-button held even

after tSRD expires

therefore RST is asserted

INT can go high , if PB goes high,

but system freezes and processor

won’t respond

if system freezes, processor won’t

respond to any INT status change

tINT _Min

tDEBOUNCE

After tON _BLANK

PB is monitored

for falling edge

ON _BLANK expires

HOLD

state detected as high

therefore EN remains high

AM00252v3

Note: EN is high.

SRC0 Datasheet(PDF) 24 Page - STMicroelectronics

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