ST7FOXU0 datasheet(73/123 Pages) STMICROELECTRONICS

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ST7FOXU0

On-chip peripherals

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10.2.4

Low power modes

10.2.5

Interrupts

Note:

The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt

mask in the CC register is reset (RIM instruction).

only if CK0=1 and CK1=0

10.2.6

TImer Control Status Register (ATCSR)

Reset Value: 0000 0000 (00h)

Bits 7:5 = Reserved, must be kept cleared.

Bits 4:3 = CK[1:0] Counter Clock Selection.

These bits are set and cleared by software and cleared by hardware after a reset. They

select the clock frequency of the counter.

Table 25.

Counter clock selection

Mode

Description

Slow

The input frequency is divided by 32

Wait

No effect on AT timer

Active-Halt

AT timer halted except if CK0=1, CK1=0 and OVFIE=1

Halt

AT timer halted

Interrupt Event 1)

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Exit

from

Active-Halt

Overflow Event

OVF

OVFIE

Yes

Yes2)

CMP Event

CMPFx

CMPIE

Yes

CK1

CK0

OVF

OVFIE

CMPIE

Read/Write

Counter Clock Selection

CK1

CK0

OFF

fLTIMER (1 ms timebase @ 8 MHz)

fCPU

Reserved

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