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ST7FOXU0 Datasheet(PDF) 34 Page - STMicroelectronics |
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ST7FOXU0 Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 123 page  Supply, reset and clock management ST7FOXU0 34/123 6.3.6 Multiplexed IO reset control register 1 (MUXCR1) Reset value: 0000 0000 (00h) 6.3.7 Multiplexed IO reset control register 0 (MUXCR0) Reset value: 0000 0000 (00h) Bits 15:0 = MIR[15:0] This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. These registers are one-time writable only. To configure PA3 as general purpose output: After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code. To configure PA3 as RESET: An internally generated reset (such as POR, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration. Table 7. Multiplexed IO register map and reset values 7 0 MIR15 MIR14 MIR13 MIR12 MIR11 MIR10 MIR9 MIR8 Read/write once only 7 0 MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0 Read/write once only Address (Hex.) Register Label 76 54 32 10 0047h MUXCR0 Reset Value MIR7 0 MIR6 0 MIR5 0 MIR4 0 MIR3 0 MIR2 0 MIR1 0 MIR0 0 0048h MUXCR1 Reset Value MIR15 0 MIR14 0 MIR13 0 MIR12 0 MIR11 0 MIR10 0 MIR9 0 MIR8 0 |
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