ST7FOXU0 datasheet(37/123 Pages) STMICROELECTRONICS

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ST7FOXU0

Supply, reset and clock management

37/123

6.5

6.5.1

RC calibration control/status register (RCC_CSR)

Reset value: 0000 0000 (00h)

Bits 7:2 = Reserved, forced by hardware to 0

0: Read mode

1: Write mode

Bit 1 = RCCLAT Latch Access Transfer bit: this bit is set by software.

It is cleared by hardware at the end of the programming cycle. It can only be cleared by

software if the RCCPGM bit is cleared

Bit 0 = RCCPGM Programming Control and Status bit

This bit is set by software to begin the programming cycle. At the end of the

programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

Note:

If the RCCPGM bit is cleared during the programming cycle, the memory data is not

guaranteed.

6.5.2

Main Clock Control/Status Register (MCCSR)

Reset value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable bit

This bit is read/write by software and cleared by hardware after a reset. This bit allows

to enable the MCO output clock.

0: MCO clock disabled, I/O port free for general purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow mode selection bit

This bit is read/write by software and cleared by hardware after a reset. This bit selects

the input clock fOSC or fOSC/32.

0: Normal mode (fCPU = fOSC

1: Slow mode (fCPU = fOSC/32)

000000

RCCLAT

RCCPGM

Read/write

000000

MCO

SMS

Read/write

ST7FOXU0 Datasheet(PDF) 37 Page - STMicroelectronics

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