CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

84427 DATA SHEET

4

REVISION B 5/6/15

A

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

F

OUT

Output Frequency

77.76

625

MHz

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 1

155.52MHz,

(Integration Range: 12kHz-20MHz)

3.4

ps

156.25MHz,

(Integration Range: 12kHz-20MHz)

3.1

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 2

36

ps

tsk(o)

Output Skew; NOTE 3, 4

85

ps

t

Output Rise/Fall Time

20% to 80%

200

600

ps

odc

Output Duty Cycle

47

52

%

t

LOCK

PLL Lock Time

1ms

See Parameter Measurement Information section.

NOTE 1: See Phase Noise Plots.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential crossing points.

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Frequency

19.44

25.5

MHz

Equivalent Series Resistance (ESR)

50

Ω

Shunt Capacitance

7pF

Drive Level

1mW