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LAN9252/ML Datasheet(PDF) 287 Page - Microchip Technology |
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LAN9252/ML Datasheet(HTML) 287 Page - Microchip Technology |
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287 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 287 LAN9252 12.14.83 LATCH0 CONTROL REGISTER Note: Writes to this register depend on the Latch In Unit 0 bit of the Cyclic Unit Control Register. 12.14.84 LATCH1 CONTROL REGISTER Note: Writes to this register depend on the Latch In Unit 1 bit of the Cyclic Unit Control Register. Offset: 09A8h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:2 RESERVED Write as 0. RO RO 000000b 1 LATCH0 Negative Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b 0 LATCH0 Positive Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b Offset: 09A9h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:2 RESERVED Write as 0. RO RO 000000b 1 LATCH1 Negative Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b 0 LATCH1 Positive Edge 0: Continuous Latch active 1: Single Event (only first event active) R/W R/W 0b |
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