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LMK05028RGCT.B Datasheet(PDF) 39 Page - Texas Instruments

Part # LMK05028RGCT.B
Description  LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM
PDF  94 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

LMK05028RGCT.B Datasheet(HTML) 39 Page - Texas Instruments

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7.3.8.5 Tuning Word History
Each REF-DPLL domain has a tuning word history monitor block that determines the initial output frequency
accuracy upon entry into holdover. The tuning word can be updated from one of three sources depending on the
DPLL operating mode:
1. Locked Mode: From the output of the digital loop filter when locked
2. Holdover Mode: From the final output of the history monitor
3. Free Run Mode: From the free-run tuning word register (user defined)
When the history monitor is enabled and the DPLL is locked, the monitor effectively averages the reference
input frequency by accumulating history from the digital loop filter output during a programmable averaging time
(TAVG). Once the input becomes invalid, the final tuning word value is stored to determine the initial holdover
frequency accuracy. Generally, a longer TAVG time produces a more accurate initial holdover frequency. The
stability of the 0-ppm reference clock (XO or TCXO input) determines the long-term stability and accuracy of the
holdover output frequency.
There is also a separate programmable delay timer (TIGN) that can be set to ignore the history data that is
corrupted just prior to entry into holdover. The history data can be corrupted if a tuning word update occurs
while the input clock is failing and before the input clock is detected by the input monitors. Both TAVG and TIGN
times are programmable through the HISTCNT and HISTDLY register bits, respectively, and are related to the
REF-TDC rate.
The tuning word history is initial cleared after a device hard reset or soft reset. The history monitor begins to
accumulate history once the DPLL locks to a new reference. The previous history is cleared when a switchover
to a new reference occurs assuming the history persistence bit (HIST_HOLD) is not set. The history can be
manually cleared by asserting the history soft reset bit (HIST_SW_RST). If the history persistence bit is set, the
history monitor is not clear the previous history value during reference switchover, holdover exit, or history soft
reset. Whenever the tuning word is cleared, the history monitor waits for the first TAVG timer to expire before
storing the first tuning word value.
Ref Lost
LORÆ 1
History
Reset
History Valid
Holdover
Locked
Ref Valid
LORÆ 0
Free Run
Lock Acq.
Locked
No History
Lock Acq.
Ref Valid
LORÆ 0
Initial holdover
frequency determined
by averaged history.
History Count*
Timer to average history data to
compute initial holdover frequency accuracy.
History Delay*
Delay to ignore
history updates
prior to LOR.
History held*
or cleared on
holdover exit.
Time
History Data Accumulating
LOFL = 0, LOPL = 1
LOFL = 0, LOPLÆ 0
LOFLÆ 0, then LOPLÆ 0
LOFL = 1, LOPL = 1
*Programmable
settings
LOFL = 0, LOPLÆ 1
History Data Accumulating
TAVG(0)
TAVG(1)
TAVG(2..n)
TIGN
Initial start of history
when LOFLÆ 0 only
Figure 7-23. Tuning Word History Windows
If the TAVG period is set very long (minutes or hours) to obtain a more precise historical average frequency, a
switchover or holdover event can occur before the first tuning word is stored and available for use. To overcome
this, there is an intermediate history update option (HIST_INTMD). If the history is reset, then the intermediate
average can be updated at intervals of TAVG/2K , where K = HIST_INTMD to 0, during the first TAVG period only.
If HIST_INTMD = 0, there is no intermediate update and the first average is stored after the first TAVG period.
However, if HIST_INTMD = 4, then four intermediate averages are taken at TAVG/16, TAVG/8, TAVG/4, and TAVG/2,
as well as at TAVG. After the first TAVG period, all subsequent history updates occur at the TAVG period.
When no tuning word history exists, the free-run tuning word value (TUNING_FREE_RUN) determines the initial
holdover output frequency accuracy.
www.ti.com
LMK05028
SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: LMK05028



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