LMK05028RGCT.B datasheet(78/94 Pages) TI2

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– Below the loop bandwidth, the reference noise is added to the REF-TDC noise floor (and the XO noise

in 2-loop mode). Above the loop bandwidth, the reference noise is attenuated with roll-off up to 60

dB/decade. The optimal bandwidth depends on the relative phase noise between the reference input

and the XO (2-loop mode) or the TCXO (3-loop mode).

– 3-Loop mode: The bandwidth is typically 10 mHz to 10 Hz to attenuate wander, or determined by the

applicable standard specification.

– 2-Loop mode: The bandwidth is typically 10 Hz or higher. Target a bandwidth below 200 Hz if the PLL

VCO frequency is an integer multiple of the reference input frequency.

• TICS Pro: Configure the TCXO-DPLL loop bandwidth.

– The optimal bandwidth depends on the relative phase noise between the TCXO/OCXO and the XO.

Below the loop bandwidth, the TCXO/OCXO noise is added to the TCXO-TDC noise floor. Above the

loop bandwidth, the OCXO/TCXO noise is attenuated.

– 3-Loop mode: The bandwidth must be at least 50x higher than the REF-DPLL bandwidth for loop

stability.

– 2-Loop TCXO-DPLL mode: Target a bandwidth below 300 Hz if the PLL VCO frequency is an integer

multiple of the TCXO/OCXO frequency.

• TICS Pro: Configure the Market Segment parameter to optimize the DPLL for the desired use case.

– SyncE/SONET: REF-TDC rate is targeted for approximately 400 kHz. Hitless switching is enabled.

This supports SyncE/SONET and other use cases using a narrow loop bandwidth (≤10 Hz) in 3-loop

mode with a TCXO/OCXO to set the frequency stability and wander performance.

– Wireless/BTS: REF-TDC rate is maximized for lowest in-band TDC noise contribution. Hitless

switching is enabled. Supports wireless and other use cases where close-in phase noise is critical.

This is used to achieve –112 dBc/Hz at 100-Hz offset for a 122.88-MHz output.

– OTN/JitterAtten: REF-TDC rate is targeted for approximately 1 MHz. Hitless switching is disabled.

Supports OTN/OTU and traditional jitter cleaning use cases with wider bandwidths (>10 Hz) in 2-loop

mode and relaxed holdover frequency accuracy (no TCXO/OCXO).

• TICS Pro: If clock steering is needed (such as for IEEE 1588 PTP), configure DCO mode for the

REF or TCXO loop and enter the frequency step size (in ppb). The FDEV step register is computed

according to DCO Frequency Step Size. To allow DCO frequency updates using the external control pins,

enable the FINC/FDEC functionality on the needed GPIO pins by setting the appropriate register bits

(GPIO[3:6]_FDEV_EN).

• TICS Pro: If deterministic input-to-output clock phase is needed, configure Zero-Delay mode and select

the primary output channel that must be phase-aligned with the input. For DPLL1, any output from the

OUT[4:7] bank can be selected for zero-delay feedback. For DPLL2, any output from the OUT[0:3] bank

can be selected for zero-delay feedback. See Zero-Delay Mode (ZDM) Configuration.

6. TICS Pro: Configure the reference input monitoring options for each reference input. Disable the monitor

when not required or when the input operates beyond the monitor's supported frequency range. See

Reference Input Monitoring.

• Amplitude monitor: Set the LVCMOS detected slew rate edge or the differential input amplitude threshold

to monitor input signal quality. Disable the monitor for a differential input below 5 MHz or else use

LVCMOS input clock.

• Frequency monitor: Set the valid and invalid thresholds (in ppm).

• Missing pulse monitor: Set the late window threshold (TLATE) to allow for the longest expected input clock

period, including worst-case cycle-to-cycle jitter. For a gapped clock input, set TLATE based on the number

of allowable missing clock pulses.

• Runt pulse monitor: Set the early window threshold (TEARLY) to allow for the shortest expected input clock

period, including worst-case cycle-to-cycle jitter.

• Validation timer: Set the amount of time the reference input must be qualified by all enabled input

monitors before the input is valid for selection.

7. TICS Pro: Configure the DPLL lock detect and tuning word history monitoring options for each channel. See

PLL Lock Detectors and Tuning Word History.

• DPLL tuning word history: Set the history count/averaging time (TAVG), history delay/ignore time (TIGN),

and intermediate averaging option.

• DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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