LMK05028RGCT.B datasheet(6/94 Pages) TI2

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4.1 Device Start-Up Modes

The HW_SW_CTRL input pin selects the device start-up mode that determines the memory page used to

initialize the registers, serial interface, and logic pin functions at power-on reset. The initial register settings

determine the device's frequency configuration stored in the internal EEPROM (NVM) or ROM. After start-up,

the device registers can be accessed through the selected serial interface for device status monitoring or

programming, and the logic pins will function as defined by the mode configuration.

Table 4-2. Device Start-Up Modes

HW_SW_CTRL

INPUT LEVEL(1)

START-UP MODE

MODE DESCRIPTION

EEPROM + I2C

(Soft pin mode)

Registers are initialized from EEPROM, and I2C interface is enabled. Logic pins:

•

SDA, SCL: I2C Data, I2C Clock (open-drain). Pins require external pullups > 1 kΩ.

•

GPIO0: Output SYNC Input (active low). Tie pin high externally if not used.

•

GPIO[2:1](1): I2C Address LSB Select Input (00, 01, 10, 11b)

•

GPIO[4:3](2): DPLL1 DCO Frequency Decrement and Increment Inputs (active high)

•

GPIO[6:5](2) (3): DPLL2 DCO Frequency Decrement and Increment Inputs (active high), or

Status Outputs

Float

(VIM)

EEPROM + SPI

(Soft pin mode)

Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:

•

SDA, SCL: SPI Data Input (SDI), SPI Clock (SCK)

•

GPIO1: SPI Chip Select (SCS)

•

GPIO2: SPI Data Output (SDO)

•

GPIO[6:3, 0]: Same as for HW_SW_CTRL = 0

ROM + I2C

(Hard pin mode)

Registers are initialized from the ROM page selected by GPIO pins, and I2C interface is enabled.

Logic pins:

•

SDA, SCL: I2C Data, I2C Clock (open-drain). Pins require external pullups > 1 kΩ.

•

GPIO[3:0](1): ROM Page Select Input (0000 to 1111b)

•

GPIO[6:5](3): Status Outputs

•

GPIO4: Not used during POR

After POR, GPIO[6:3] can function the same as for HW_SW_CTRL = 0 if enabled by registers.

(1)

The input levels on these pins are sampled only during POR.

(2)

These GPIO pins are only functional when the DCO feature and FINC/FDEC pin controls are enabled by registers.

(3)

As status outputs, the GPIO[6:5] pins have the same configuration options as the STATUS[1:0] pins.

Note

To provide proper start-up into EEPROM + SPI Mode, the HW_SW_CTRL, STATUS0, and STATUS1

pins must all be floating or biased to VIM (0.8-V typical) before the PDN pin is pulled high. These three

pins momentarily operate as 3-level inputs and get sampled at the low-to-high transition of PDN to

determine the device start-up mode during POR. If any of these pins are connected to a host device

(MCU or FPGA), TI recommends using external biasing resistors on each pin (10-kΩ pullup to 3.3 V

with 3.3-kΩ pulldown to GND) to set the inputs to VIM during POR. After power-up, the STATUS pins

can operate as LVCMOS outputs to overdrive the external resistor bias for normal status operation.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

www.ti.com

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