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HS4318ESS01H Datasheet(PDF) 48 Page - Renesas Technology Corp |
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HS4318ESS01H Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 68 page  HD404318 Series 46 Transmit clock erors are detected as illustrated in figure 37. Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Transmit clock error processing Normal termination ← ← Yes No Transmit clock error detection flowchart Transmit clock error detection procedure State SCK pin (input) Transmit clock wait state Transfer state Transfer state Transmit clock wait state Noise Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. Flag set because octal counter reaches 000. Flag reset at transfer completion. SMR write IFS 12 3 4 56 78 Figure 37 Transmit Clock Error Detection |
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