Single-Phase Power-Measurement

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Table 3. DSPCFG Register Detail

BIT

NAME

DESCRIPTION

0

DISIL

1 = disable IL measurements

0 = enable IL measurements (default)

1

RESERVED

Must be set to 1

2

RESERVED

Must be set to 0

3

PECEN

4

AVGP

1 = Begin accumulating PAVG

0 = Stop accumulating PAVG (default)

5

AVGRD

1 = PAVG calculation complete

0 = PAVG calculation in progress, following AVGP 1 R 0

(This bit is automatically cleared the next time the master sets AVGP to 1.)

6

PWMOUT

1 = AUX pin outputs in PWM format

0 = AUX pin outputs in digital format (default)

7

DISPGA

1 = Disable gain switching

0 = Enable gain switching (recommended, default)

8

ILPGA

1 = PGA for IL = x4 (default)

0 = PGA for IL = x1

9

ACMODE

1 = AC mode

0 = DC mode (default)

10:11

RESERVED

—

12:15

RESET_STATUS

Reset Status Indicator. These bits allow the master to determine if the MAXQ314 has per-

formed a reset since the last time these bits were cleared. When these bits are 1111, the

MAXQ314 has performed a reset. After the bits have been read, the master must write 0000

to these bits to clear the reset indicator. Writing to and reading from these bits does not

affect processor operation or cause a reset; they are only status bits.